View CY7C1393AV18-167BZC_3053390.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary 18-mbit ddr-ii sio sram 2-word burst architecture cy7c1392av18 cy7c1393av18 cy7c1394av18 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05503 rev. *a revised june 1, 2004 features ? 18-mbit density (2m x 8, 1m x 18, 512k x 36) ? 250-mhz clock for high bandwidth ? 2-word burst for reducing address bus frequency ? double data rate (ddr) interfaces (data transferred at 500 mhz) @ 250 mhz ? two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only ? two output clocks (c and c ) account for clock skew and flight time mismatching ? echo clocks (cq and cq ) simplify data capture in high-speed systems ? synchronous internally self-timed writes ? 1.8v core power supply with hstl inputs and outputs ? variable drive hstl output buffers ? expanded hstl output voltage (1.4v?v dd ) ? 13 x 15 x 1.4mm 1.0-mm pitch fbga package, 165 ball (11 x 15 matrix) ? jtag 1149.1 compatible test access port ? delay lock loop (dll) for accurate data placement configuration cy7c1392av18?2m x 8 cy7c1393av18?1m x18 cy7c1394av18?512k x 36 functional description the cy7c1392av18/cy7c1393av18/cy7c1394av18 are 1.8v synchronous pipelined srams equipped with ddr-ii sio (double data rate separate i/o) architecture. the ddr-ii sio consists of two separate ports to access the memory array. the read port has dedicated data outputs and the write port has dedicated data inputs to completely eliminate the need to ?turn around? the dat a bus required with common i/o devices. access to each port is accomplished using a common address bus. addresses for read and write are latched on alternate rising edges of the input (k) clock. write data is regis- tered on the rising edges of both k and k . read data is driven on the rising edges of c and c if provided, or on the rising edge of k and k if c/c are not provided. each address location is associated with two 8-bit words in the case of cy7c1392av18, two 18-bit words in the case of cy7c1393av18, and two 36-bit words in the case of cy7c1394av18, that burst sequentially into or out of the device. asynchronous inputs include impedance match (zq). synchronous data outputs are tightly matched to the two output echo clocks cq/cq , eliminating the need for separately capturing data from each individual ddr-ii sio sram in the system design. output data clocks (c/c ) enable maximum system clocking and data sy nchronization flexibility. all synchronous inputs pass through input registers controlled by the k/k input clocks. all data outputs pass through output registers controlled by the c/c input clocks (or k/k in single clock mode). writes are conducted with on-chip synchronous self-timed write circuitry. l og i c bl oc k di agram (cy7c1392av18) 1m x 8 clk a (19:0) gen. k k control logic address register d [7:0] read add. decode read data reg. ld q [7:0] control logic reg. reg. reg. 8 8 16 write 8 bws 0 v ref write add. decode data reg write data reg memory array 1m x 8 memory array 8 8 20 8 c c bws 1 r/w ld r/w cq cq doff
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 2 of 21 selection guide 250 mhz 200 mhz 167 mhz unit maximum operating frequency 250 200 167 mhz maximum operating current 800 750 700 ma logic block diagram (cy7c1393av18) 512k x 18 clk a (18:0) gen. k k control logic address register d [17:0] read add. decode read data reg. ld q [17:0] control logic reg. reg. reg. 18 18 36 write 18 bws 0 v ref write add. decode data reg write data reg memory array 512k x 18 memory array 18 18 19 18 c c bws 1 r/w ld r/w cq cq doff logic block diagram (cy7c1394av18) 256k x 36 clk a (17:0) gen. k k control logic address register d [35:0] read add. decode read data reg. ld q [35:0] control logic reg. reg. reg. 36 36 72 write 36 bws [3:0] v ref write add. decode data reg write data reg memory array 256k x 36 memory array 36 36 18 36 c c r/w ld r/w cq cq doff
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 3 of 21 pin configurations cy7c1392av18 (2m 8) ? 11 15 fbga 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc v ss /72m a bws 1 k r/w nc nc nc nc nc nc tdo nc nc d5 nc nc nc tck nc nc a nc k bws 0 v ss aaa nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd q4 nc v ddq nc nc nc nc q7 a v ddq v ss v ddq v dd v dd q5 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d4 v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss c nc q6 nc d7 d6 v dd a 891011 nc av ss /36m ld cq a nc nc q3 v ss nc nc d3 nc v ss nc q2 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq d1 v ddq nc q1 nc v ddq v ddq nc v ss nc d0 nc tdi tms v ss a nc a nc d2 nc zq nc q0 nc nc nc nc a cy7c1393av18 (1m 18) ? 11 15 fbga 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc v ss /144m nc/36m bws 1 k r/w nc q9 d9 nc nc nc tdo nc nc d13 nc nc nc tck nc d10 a nc k bws 0 v ss aaa q10 v ss v ss v ss v ss v dd a v ss v ss v ss v dd q11 d12 v ddq d14 q14 d16 q16 q17 a v ddq v ss v ddq v dd v dd q13 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d11 v ss nc v ss q12 nc v ref v ss v dd v ss v ss a v ss c nc q15 nc d17 d15 v dd a 891011 q0 av ss /72m ld cq a nc nc q8 v ss nc q7 d8 nc v ss nc q6 d5 nc nc v ref nc q3 v ddq nc v ddq nc q5 v ddq v ddq v ddq d4 v ddq nc q4 nc v ddq v ddq nc v ss nc d2 nc tdi tms v ss a nc a d7 d6 nc zq d3 q2 d1 q1 d0 nc a
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 4 of 21 pin definitions pin name i/o pin description d [x:0] input- synchronous data input signals, sampled on the rising edge of k and k clocks during valid write operations . cy7c1392av18 ? d [7:0] cy7c1393av18 ? d [17:0] cy7c1394av18 ? d [35:0] ld input- synchronous synchronous load : this input is brought low when a bus cycle sequence is to be defined. this definition includes address and read/write di rection. all transactions operate on a burst of 2 data (one period of bus activity). bws [3:0] input- synchronous byte write select 0, 1, 2, and 3 ? active low . sampled on the rising edge of the k and k clocks during write operations. used to select which byte is written into the device during the current portion of the write operatio ns. bytes not written remain unaltered. cy7c1392av18 ? bws 0 controls d [3:0] and bws 1 controls d [7:4] . cy7c1393av18 ? bws 0 controls d [8:0] and bws 1 controls d [17:9]. cy7c1394av18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18] and bws 3 controls d [35:27] all the byte write selects are sampled on the sa me edge as the data. deselecting a byte write select will cause the corresponding byte of data to be ignored and not written into the device. a input- synchronous address inputs . sampled on the rising edge of the k clock during active read and write operations. these address inputs are multiplexed for both read and write operations. internally, the device is organized as 2m x 8 (2 arrays each of 1m x 8) for cy7c1392av18, 1m x 18 (two arrays each of 512k x 18) for cy7c1393av18 and 512k x 36 (2 arrays each of 256k x 36) for cy7c1394av18. therefore only 20 address inputs are needed to access the entire memory array of cy7c1392av18, 19 address inputs for cy7c1393av18, and 18 address inputs for cy7c1394av18. these inputs are ignored wh en the appropriate port is deselected. q [x:0] output- synchronous data output signals . these pins drive out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read operations or k and k when in single clock mode. when read access is deselected, q [x:0] are automatically three-stated. cy7c1392av18 ? q [7:0] cy7c1393av18 ? q [17:0] cy7c1394av18 ? q [35:0] pin configurations (continued) cy7c1394av18 (512k 36) ? 11 15 fbga 234 567 1 a b c d e f g h j k l m n p r a cq q27 d27 d28 d34 doff q33 v ss /288m nc/72m bws 2 k r/w bws 1 q18 d18 q30 d31 d33 tdo q28 d29 d22 d32 q34 q31 tck d35 d19 a bws 3 k bws 0 v ss aaa q19 v ss v ss v ss v ss v dd a v ss v ss v ss v dd q20 d21 v ddq d23 q23 d25 q25 q26 a v ddq v ss v ddq v dd v dd q22 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a d20 v ss q29 v ss q21 d30 v ref v ss v dd v ss v ss a v ss c q32 q24 q35 d26 d24 v dd a 891011 q0 nc/36m v ss /144m ld cq a d17 q17 q8 v ss d16 q7 d8 q16 v ss d15 q6 d5 d9 q14 v ref q11 q3 v ddq q15 v ddq d14 q5 v ddq v ddq v ddq d4 v ddq d12 q4 q12 v ddq v ddq d11 v ss d10 d2 q10 tdi tms v ss a q9 a d7 d6 d13 zq d3 q2 d1 q1 d0 q13 a
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 5 of 21 r/w input- synchronous synchronous read/write input : when ld is low, this input designates the access type (read when r/w is high, write when r/w is low) for loaded address. r/w must meet the set-up and hold times around edge of k. c input- clock positive output clock input . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the fl ight times of various devices on the board back to the controller. see application example for further details. c input- clock negative output clock input . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the fl ight times of various devices on the board back to the controller. see application example for further details. k input- clock positive input clock input . the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k input- clock negative input clock input . k is used to capture synchronous inputs being presented to the device and to drive out data through q [x:0] when in single clock mode. cq echo clock cq is referenced with respect to c . this is a free-running clock and is synchronized to the output clock (c) of the ddr-ii. in the single clock mode, cq is generated with respect to k. the timings for the echo clocks are s hown in the ac timing table. cq echo clock cq is referenced wi th respect to c . this is a free-running clock and is synchronized to the output clock (c ) of the ddr-ii. in the single clock mode, cq is generated with respect to k . the timings for the echo clocks are s hown in the ac timing table. zq input output impedance matching input . this input is used to tune the device outputs to the system data bus impedance. cq, cq , and q [x:0] output impedance are set to 0.2 x rq, where rq is a resistor connected between zq a nd ground. alternately, this pi n can be connected directly to v dd , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected. doff input dll turn off, active low . connecting this pin to ground will turn off the dll inside the device. the timings in the dll turned off operation will be different from those listed in this data sheet. more details on this operation can be found in the application note dll operation in the qdr?-ii . tdo output tdo for jtag . tck input tck pin for jtag . tdi input tdi pin for jtag . tms input tms pin for jtag . nc/36m n/a address expansion for 36m . this is not connected to the die and so can be tied to any voltage level. v ss /36m input address expansion for 36m . this should be tied low. nc/72m n/a address expansion for 72m . this is not connected to the die and so can be tied to any voltage level. v ss /72m input address expansion for 72m . this must be tied low. v ss /144m input address expansion for 144m . this must be tied low. v ss /288m input address expansion for 288m . this must be tied low. v ref input- reference reference voltage input . static input used to set the reference level for hstl inputs and outputs as well as ac measurement points. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq power supply power supply inputs for the outputs of the device . nc n/a not connected to the die . can be tied to any voltage level. pin definitions (continued) pin name i/o pin description
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 6 of 21 introduction functional overview the cy7c1392av18/cy7c1393av18/cy7c1394av18 are synchronous pipelined burst srams equipped with a ddr-ii separate i/o interface. accesses are initiated on the rising edge of the positive input clock (k). all synchronous input timing is referenced from the rising edge of the input clocks (k and k ) and all output timing is referenced to the rising edge of the out put clocks, c/c (or k/k when in single clock mode). all synchronous data inputs (d [x:0] ) pass through input registers controlled by the risi ng edge of input clocks (k and k ). all synchronous data outputs (q [x:0] ) pass through output registers controlled by the rising edge of the output clocks, c/c (or k/k when in single clock mode). all synchronous control (r/w , ld , bws [x:0] ) inputs pass through input registers controlled by the rising edge of the input clock (k). cy7c1393av18 is described in the following sections. the same basic descriptions apply to cy7c1392av18 and cy7c1394av18. read operations the cy7c1393av18 is organized internally as two arrays of 512k x 18. accesses are completed in a burst of two sequential 18-bit data words. read operations are initiated by asserting r/w high and ld low at the rising edge of the positive input clock (k). the address presented to the address inputs is stored in the read address register. following the next k clock rise the corresponding lowest-order 18-bit word of data is driven onto the q [17:0] using c as the output timing reference. on the subsequent ri sing edge of c the next 18-bit data word is driven onto the q [17:0] . the requested data will be valid 0.45 ns from the rising edge of the output clock (c or c , or k or k when in single clock mode, for 250-mhz and 200-mhz devices). read accesses can be initiated on every k clock rise. doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks, c/c (or k/k when in single clock mode). when read access is deselected, the cy7c1393av18 will first complete the pending read transactions. synchronous internal circuitry will automatically thre e-state the outputs following the next rising edge of the positive output clock (c). write operations write operations are initiated by asserting r/w low and ld low at the rising edge of the positive input clock (k). on the following k clock rise the data presented to d [17:0] is latched and stored into the lower 18-bit write data register provided bws [1:0] are both asserted active . on the subsequent rising edge of the negative input clock (k ), the information presented to d [17:0] is also stored into the write data register provided bws [1:0] are both asserted acti ve. write accesses can be initiated on every rising edge of input clock (k). doing so pipelines the data flow so that 18 bits of data are written into the device on every rising edge of both input clocks (k and k ). when write access is deselected, the device will ignore all data inputs after the pending write operations have been completed. byte write operations byte write operations are supported by the cy7c1393av18. a write operation is initiated as described in the write operation section above. the bytes that are written are deter- mined by bws 0 and bws 1 , which are sampled with each set of 18-bit data words. asserting the appropriate byte write select input during the data port ion of a write will allow the data being presented to be latched and written into the device. deasserting the byte write sele ct input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. this feat ure can be used to simplify read/modify/write operations to a byte write operation. single clock mode the cy7c1393av18 can be used with a single clock that controls both the input and output registers. in this mode the device will recognize only a single pair of input clocks (k and k ) that control both the input and output registers. this operation is identical to the operation if the device had zero skew between the k/k and c/c clocks. all timing parameters remain the same in this mode. to use this mode of operation, the user must tie c and c high at power-on. this function is a strap option and not alterable during device operation. the echo clocks are synchroniz ed to input clocks k/k in this mode. ddr operation the cy7c1393av18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double ddr mode of operation. if a read occurs after a write cycle, address and data for the write are stored in registers. the write information must be stored because the sram can not perform the last word write to the array without conflicting with the read. the data stays in this register until the next write cycle o ccurs. on the first write cycle after the read(s), the stored data from the earlier write will be written into the sram array. this is called a posted write. depth expansion depth expansion require s replicating the ld control signal for each bank. all other control signals can be common between banks as appropriate. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the va lue of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance matching with a tolerance of 15% is between 175 ? and 350 ? , with v ddq = 1.5v. the output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. echo clocks echo clocks are provided on th e ddr-ii to simplify data capture on high-speed system s. two echo clocks are generated by the ddr-ii. cq is referenced with respect to c and cq is referenced with respect to c . these are free-running clocks and are syn chronized to t he output clock of the separate i/o ddr. in the single clock mode, cq is generated with respect to k and cq is generated with respect to k . the timings for the echo clocks are shown in the ac timing table. dll these chips utilize a delay lock loop (dll) that is designed to function between 80 mhz and the specified maximum clock frequency. the dll may be disabled by applying ground to the doff pin. the dll can also be re set by slowing the cycle time of input clocks k and k to greater than 30 ns.
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 7 of 21 application example [1] truth table [2, 3, 4, 5, 6, 7] operation k ld r/w dq dq write cycle: load address; wait one cycle; input write data on consecutive k and k rising edges. l-h l l d(a + 0)at k(t + 1) d(a + 1) at k (t + 1) read cycle: load address; wait one and a half cycle; read data on consecutive c and c rising edges. l-h l h q(a + 0) at c (t + 1) q(a + 1) at c(t + 2) nop: no operation l-h h x high-z high-z standby: clock stopped stopped x x previous state previous state write cycle descriptions (cy7c1392av18 and cy7c1393av18) [2, 8] bws 0 bws 1 kk comments l l l-h - during the data portion of a write sequence : cy7c1392av18 ? both nibbles (d [7:0] ) are written into the device, cy7c1393av18 ? both bytes (d [17:0] ) are written into the device. l l - l-h during the data portion of a write sequence : cy7c1392av18 ? both nibbles (d [7:0] ) are written into the device, cy7c1393av18 ? both bytes (d [17:0] ) are written into the device. l h l-h - during the data portion of a write sequence : cy7c1392av18 ? only the lower nibble (d [3:0] ) is written into the device. d [7:4] will remain unaltered, cy7c1393av18 ? only the lower byte (d [8:0] ) is written into the device. d [17:9] will remain unaltered. l h - l-h during the data portion of a write sequence : cy7c1392av18 ? only the lower nibble (d [3:0] ) is written into the device. d [7:4] will remain unaltered, cy7c1393av18 ? only the lower byte (d [8:0] ) is written into the device. d [17:9] will remain unaltered. notes: 1. the above application shows four ddr-ii sio being used. 2. x = ?don't care,? h = logic high, l = logic low, represents rising edge. 3. device will power-up deselected and the outputs in a three-state condition. 4. ?a? represents address location latched by the devices when transaction was initiated. a + 0, a + 1 represents the internal a ddress sequence in the burst. 5. ?t? represents the cycle at which a read/write operation is started. t+1, t + 2 and t +3 are the first, second and third cloc k cycles succeeding the ?t? clock cycle. 6. data inputs are registered at k and k rising edges. data outputs are delivered on c and c rising edges, except when in single clock mode. 7. it is recommended that k = k and c = c = high when clock is stopped. this is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. assumes a write cycle was initiated per the write cycle description truth table. bws 0 , bws 1 in the case of cy7c1392av18 and cy7c1393av18 and also bws 2 , bws 3 in the case of cy7c1394av18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved. ld # r/w # b w # vt = v ref cc# cq cq# k# zq q d k cc# k bus master (cpu or asic) sram 1 sram 4 data in data out address ld# r/w# bws# sram 1 input cq sram 1 input cq# sram 4 input cq sram 4 input cq# source k source k# delayed k delayed k# r = 50 ohms r = 250 ohms cq cq# k# zq q ld # r/w # b w s # ld # r/w # vt vt vt r r r a a d r = 250 ohms b w s #
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 8 of 21 h l l-h ? during the data portion of a write sequence : cy7c1392av18 ? only the upper nibble (d [7:4] ) is written into the device. d [3:0] will remain unaltered, cy7c1393av18 ? only the upper byte (d [17:9] ) is written into the device. d [8:0] will remain unaltered. h l ? l-h during the data portion of a write sequence : cy7c1392av18 ? only the upper nibble (d [7:4] ) is written into the device. d [3:0] will remain unaltered, cy7c1393av18 ? only the upper byte (d [17:9] ) is written into the device. d [8:0] will remain unaltered. h h l-h ? no data is written into the devices during this portion of a write operation. h h ? l-h no data is written into the devices during this portion of a write operation. write cycle descriptions (cy7c1394av18) [2, 8] bws 0 bws 1 bws 2 bws 3 kk comments l l l l l-h ? during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l l l l ? l-h during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l-h - during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] will remain unaltered. l h h h ? l-h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] will remain unaltered. h l h h l-h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] will remain unaltered. h l h h ? l-h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] will remain unaltered. h h l h l-h ? during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] will remain unaltered. h h l h ? l-h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] will remain unaltered. h h h l l-h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] will remain unaltered. h h h l ? l-h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] will remain unaltered. hhhhl-h?no data is written into the device during this portion of a write operation. hhhh?l-hno data is written into the device during this portion of a write operation. write cycle descriptions (cy7c1392av18 and cy7c1393av18) (continued) [2, 8] bws 0 bws 1 kk comments
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 9 of 21 maximum ratings (above which the useful life may be impaired.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with powe r applied .. ?55c to +125c supply voltage on v dd relative to gnd........ ?0.5v to +2.9v dc voltage applied to outputs in high-z state .................................... ?0.5v to v ddq + 0.5v dc input voltage [9] .............................. ?0.5v to v ddq + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage (m il-std-883, m 3015)... > 2001v latch-up current.................................................... > 200 ma operating range range ambient temperature v dd [10] v ddq [10] com?l 0c to +70c 1.8 0.1v 1.4v to v dd electrical characteristics over the operating range [11] dc electrical characteristics parameter description test conditions min. typ. max. unit v dd power supply voltage 1.7 1.8 1.9 v v ddq i/o supply voltage 1.4 1.5 v dd v v oh output high voltage note 12 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v ol output low voltage note 13 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ? 0.1 ma, nominal impedance v ddq ? 0.2 v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss 0.2 v v ih input high voltage [9] v ref + 0.1 v ddq + 0.3 v v il input low voltage [9, 14] ?0.3 v ref ? 0.1 v v in clock input voltage ?0.3 v ddq + 0.3 v i x input load current gnd v i v ddq ?5 5 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a v ref input reference voltage [15] typical value = 0.75v 0.68 0.75 0.95 v i dd v dd operating supply v dd = max.,i out = 0 ma, f = f max = 1/t cyc 167 mhz 700 ma 200 mhz 750 ma 250 mhz 800 ma i sb1 automatic power-down current max. v dd , both ports deselected, v in v ih or v in v il ,f = f max = 1/t cyc , inputs static 167 mhz 450 ma 200 mhz 470 ma 250 mhz 490 ma ac input requirements parameter description test conditions min. typ. max. unit v ih input high (logic 1) voltage v ref + 0.2 ? ? v v il input low (logic 0) voltage ? ? v ref ? 0.2 v thermal resistance [16] parameter description test conditions 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 16.7 c/w jc thermal resistance (junction to case) 2.5 c/w notes: 9. overshoot: v ih (ac) < v dd +0.85v (pulse width less than t tcyc /2); undershoot v il (ac) > ?1.5v (pulse width less than t tcyc /2). 10. power-up: assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . 11. all voltage referenced to ground. 12. outputs are impedance controlled. i oh = ?(v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 13. outputs are impedance controlled. i ol =(v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 14. this spec is for all inputs except c and c clock. for c and c clock, v il (max.) = v ref ? 0.2v. 15. v ref (min.) = 0.68v or 0.46v ddq , whichever is larger, v ref (max.) = 0.95v or 0.54v ddq , whichever is smaller. 16. tested initially and after any design or process change that may affect these parameters.
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 10 of 21 capacitance [16] parameter description tes t conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 1.8v v ddq = 1.5v 5pf c clk clock input capacitance 6 pf c o output capacitance 7 pf ac test loads and waveforms switching characteristics over the operating range [17, 18] cypress parameter consortium parameter description 250 mhz 200 mhz 167 mhz unit min. max. min. max. min. max. t cyc t khkh k clock and c clock cycle time 4.0 6.3 5.0 7.9 6.0 8.4 ns t kh t khkl input clock (k/k and c/c ) high 1.6 ? 2.0 ? 2.4 ? ns t kl t klkh input clock (k/k and c/c ) low 1.6 ? 2.0 ? 2.4 ? ns t khk h t khk h k clock rise to k clock rise and c to c rise (rising edge to rising edge) 1.8 ? 2.2 ? 2.7 ? ns t khch t khch k/k clock rise to c/c clock rise (rising edge to rising edge) 0.0 1.8 0.0 2.3 0.0 2.8 ns set-up times t sa t sa address set-up to k clock rise 0.5 ? 0.6 ? 0.7 ? ns t sc t sc control set-up to clock (k, k ) rise (ld , r/w ) 0.5 ? 0.6 ? 0.7 ? ns t scddr t sc double data rate control set-up to clock (k, k ) rise (bws 0 , bws 1, bws 2 , bws 3 ) 0.35 ? 0.4 ? 0.5 ? ns t sd t sd d [x:0] set-up to clock (k and k ) rise 0.35 ? 0.4 ? 0.5 ? ns hold times t ha t ha address hold after clock (k and k ) rise 0.5 ? 0.6 ? 0.7 ? ns t hc t hc control hold after clock (k and k ) rise (ld , r/w ) 0.5 ? 0.6 ? 0.7 ? ns t hcddr t hc double data rate control hold after clock (k and k ) rise (bws 0 , bws 1, bws 2 , bws 3 ) 0.35 ? 0.4 ? 0.5 ? ns t hd t hd d [x:0] hold after clock (k and k ) rise 0.35 ? 0.4 ? 0.5 ? ns output times t co t chqv c/c clock rise (or k/k in single clock mode) to data valid ?0.45?0.45?0.50ns t doh t chqx data output hold after output c/c clock rise (active to active) ?0.45 ? ?0.45 ? ?0.50 ? ns notes: 17. all devices can operate at clock frequencies as low as 119 mhz. when a part with a maximum frequency above 133 mhz is operat ing at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range. 18. unless otherwise noted, test conditions assume signal trans ition time of 2v/ns, timing reference levels of 0.75v, v ref = 0.75v, rq = 250 ? , v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads. 1.25v 0.25v r = 50 ? 5pf including jig and scope all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75v v ref = 0.75v [15] 0.75v under te s t 0.75v device under te s t output 0.75v v ref v ref output zq zq (a) rq = 250 ? (b) rq = 250 ? slew rate = 2v / ns
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 11 of 21 t ccqo t chcqv c/c clock rise to echo clock valid ? 0.45 ? 0.45 ? 0.50 ns t cqoh t chcqx echo clock hold after c/c clock rise ?0.45 ? ?0.45 ? ?0.50 ? ns t cqd t cqhqv echo clock high to data change ? 0.30 ? 0.35 ? 0.40 ns t cqdoh t cqhqx echo clock high to data change ?0.30 ? ?0.35 ? ?0.40 ? ns t chz t chz clock (c and c ) rise to high-z ( active to high-z) [19, 20] ?0.45?0.45?0.50ns t clz t clz clock (c and c ) rise to low-z [19, 20] ?0.45 ? ?0.45 ? ?0.50 ? ns dll timing t kc var t kc var clock phase jitter ? 0.20 ? 0.20 ? 0.20 ns t kc lock t kc lock dll lock time (k, c) 1024 ? 1024 ? 1024 ? cycles t kc reset t kc reset k static to dll reset 30 30 30 ns notes: 19. t chz , t clz , are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 100 mv from steady-state voltage. 20. at any given voltage and temperature t chz is less than t clz and t chz less than t co . switching characteristics over the operatin g range (continued) [17, 18] cypress parameter consortium parameter description 250 mhz 200 mhz 167 mhz unit min. max. min. max. min. max.
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 12 of 21 switching waveforms [21, 22, 23] notes: 21. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, i.e., a0+1. 22. output are disabled (high-z) one clock cycle after a nop. 23. in this example, if address a2 = a1,then data q20 = d10 and q21 = d11. write data is forwarded immediately as read results. this note applies to the whole diagram k 1 23456 78 k # l d # r /w # a q d c c # r e ad ( bu r s t of 2 ) r e ad ( bu r s t of 2 ) r e ad ( bu r s t of 2 ) w r i t e ( bu r s t of 2 ) w r i t e ( bu r s t of 2 ) q40 t kh t khkh t khch t co t kl t cyc t t hc t sa t ha t sd t hd t khch n o p t sd t hd don?t care undefined t clz t doh t clz sc t kh t khkh t kl t cyc a0 q00 q11 q01 q10 qx2 t co t cqd t doh a1 a2 a3 a4 q41 d20 d21 d30 d31 n o p c q c q # t ccqo t cqoh t ccqo t cqoh
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 13 of 21 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. this part is fully compliant with ieee standard #1149.1-1900. the tap operates using jedec standard 1.8v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signific ant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is ac tive depending upon the current state of the tap state machine (see instruction codes). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v ss ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected betw een the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register s. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. seve ral no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction code table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this stat e, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr st ate. the idcode instruction
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 14 of 21 is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction caus es the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high-z state until the next command is given during the ?update ir? state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the in- struction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is cap- tured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possi- ble that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sampl e/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bound- ary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri- or to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required?that is, while data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system out put pins. this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bu s three-state ieee standard 1149.1 mandates that t he tap controller be able to put the output bus into a three-state mode. the boundary scan register has a special bit located at bit #47. when this scan cell, called the ?extest output bus three-state?, is latched into the preload register during the ?update-dr? state in the tap controller, it will directly control the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it will enable the output buffers to drive the output bus. when low, this bit will place the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? stat e. during ?update-dr?, the value loaded into that shift-register cell will latch into the preload register. when the extest instru ction is entered, this bit will directly control the output q-bu s pins. note that this bit is pre-set high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 15 of 21 note: 24. the 0/1 next to each state represents the value at tms at the rising edge of tck. tap controller state diagram [24] test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 16 of 21 tap controller block diagram tap electrical characteristics over the operating range [11, 9, 25] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 2.0 ma 1.4 v v oh2 output high voltage i oh = ? 100 a1.6 v v ol1 output low voltage i ol = 2.0 ma 0.4 v v ol2 output low voltage i ol = 100 a0.2v v ih input high voltage 0.65v dd v dd + 0.3 v v il input low voltage ?0.3 0.35v dd v i x input and output load current gnd v i v dd ?5 5 a tap ac switching characteristics over the operating range [26, 27] parameter description min. max. unit t tcyc tck clock cycle time 100 ns t tf tck clock frequency 10 mhz t th tck clock high 40 ns t tl tck clock low 40 ns set-up times t tmss tms set-up to tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t cs capture set-up to tck rise 10 ns notes: 25. these characteristics pertain to the tap inputs (tms, tck, td i and tdo). parallel load levels are specified in the electrica l characteristics table. 26. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 27. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 106 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 17 of 21 hold times t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns tap timing and test conditions [27] tap ac switching characteristics over the operating range (continued) [26, 27] parameter description min. max. unit (a) tdo c l = 20 pf z 0 = 50 ? gnd 0.9v 50 ? 1.8v 0v all input pulses 0.9v test clock test mode select tck tms test data-in tdi test data-out t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdov t tdox tdo
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 18 of 21 identification register definitions instruction field value description cy7c1392av18 cy7c1393av18 cy7c1394av18 revision number (31:29) 000 000 000 version number. cypress device id (28:12) 11010100010000101 11010100010010101 110 10100010100101 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1 1 1 indicate the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 107 instruction codes instruction code description extest 000 captures the input/output ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the input/ou tput contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the inpu t/output ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and td o. this operation does not affect sram operation. boundary scan order bit # bump id 06r 16p 26n 37p 47n 57r 68r 78p 89r 911p 10 10p 11 10n 12 9p 13 10m 14 11n 15 9m 16 9n 17 11l 18 11m 19 9l 20 10l 21 11k 22 10k 23 9j 24 9k 25 10j 26 11j 27 11h 28 10g 29 9g boundary scan order (continued) bit # bump id
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 19 of 21 30 11f 31 11g 32 9f 33 10f 34 11e 35 10e 36 10d 37 9e 38 10c 39 11d 40 9c 41 9d 42 11b 43 11c 44 9b 45 10b 46 11a 47 internal 48 9a 49 8b 50 7c 51 6c 52 8a 53 7a 54 7b 55 6b 56 6a 57 5b 58 5a 59 4a 60 5c 61 4b 62 3a 63 1h 64 1a 65 2b 66 3b 67 1c 68 1b 69 3d 70 3c 71 1d 72 2c 73 3e boundary scan order (continued) bit # bump id 74 2d 75 2e 76 1e 77 2f 78 3f 79 1g 80 1f 81 3g 82 2g 83 1j 84 2j 85 3k 86 3j 87 2k 88 1k 89 2l 90 3l 91 1m 92 1l 93 3n 94 3m 95 1n 96 2m 97 3p 98 2n 99 2p 100 1p 101 3r 102 4r 103 4p 104 5p 105 5n 106 5r boundary scan order (continued) bit # bump id
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 20 of 21 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. qdr ? srams and quad data rate ? srams comprise a new family of products developed by cypress, hitachi, idt, micron, nec and samsung technology. all product and company names menti oned in this document are the trademarks of their respective holders. ordering information speed (mhz) ordering code package name package type operating range 250 cy7c1392av18-250bzc bb165d 13 x 15 x 1.4 mm fbga commercial cy7c1393av18-250bzc cy7c1394av18-250bzc 200 cy7c1392av18-200bzc bb165d 13 x 15 x 1.4 mm fbga commercial cy7c1393av18-200bzc cy7c1394av18-200bzc 167 cy7c1392av18-167bzc bb165d 13 x 15 x 1.4 mm fbga commercial CY7C1393AV18-167BZC cy7c1394av18-167bzc package diagram 51-85180-** 165 fbga 13 x 15 x 1.40 mm bb165d
preliminary cy7c1392av18 cy7c1393av18 cy7c1394av18 document #: 38-05503 rev. *a page 21 of 21 document history page document title: cy7c1392av18/cy7c1393av18/cy7c1394av1 8 18-mb ddr?-ii sio sram with 2-word burst archi- tecture document number: 38-05503 rev. ecn no. issue date orig. of change description of change ** 208408 see ecn dim new data sheet *a 230396 see ecn vbl upload datasheet to the internet

▲Up To Search▲

Price & Availability of CY7C1393AV18-167BZC

	To Download CY7C1393AV18-167BZC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .